1. Field of the Invention
The present invention is related to a latch circuit, and more particularly to a latch circuit receiving small amplitude signals.
2. Description of the Related Art
A circuit using a bipolar (BipTr) is employed conventionally in a semiconductor logic circuit aimed mainly at high speed operation, in which a small amplitude signal represented by an emitter coupled logic (ECL) level is employed in a latch circuit using the small amplitude signal as an input.
Referring to FIG. 8 an example of conventional latch circuit will be described. Collectors of BipTrs Q21 and Q22 which input complementary input signals EIN and EIN/ (hereinafter, the symbol "/" denotes the inversion) as their base inputs and having their emitters are connected in common, are connected to respective one side ends of resistors R21 and R22 with the respective other ends connected to the highest power supply voltage (Vcc) as well as to the bases of BipTrs Q23 and Q24 constituting an emitter follower circuit.
The emitters of BipTrs Q23 and Q24 are connected to current sources I21 and I22, respectively, and are made to be output signals EOUT and EOUT/, and the emitter potentials of the BipTrs Q23 and Q24 are input to the bases of BipTrs Q26 and Q25, respectively.
The collectors of the BipTrs Q25 and Q21, and of Q26 and Q22 are respectively connected in common. Common emitter of a current switch consisting of the BipTrs Q21 and Q22 is connected to the collector of a BipTr Q27, common emitter of a current switch consisting of the BipTrs Q25 and Q26 is connected to the collector of a BipTr Q28, common emitter of a current switch consisting of the BipTrs Q27 and Q28 is connected to a current source I23, and their bases are receiving latch switching signals ECLK and ECLK/.
Next, the operation of the circuit having a through state and a latch state shown in FIG. 8 will be described.
When the latch switching signal ECLK/ is at an active level (a high level) and the ECLK is at an inactive level (a low level), the BipTr Q27 is turned on and the BipTr Q28 is turned off, the current switch consisting of the BipTrs Q25 and Q26 is deactivated, and the current of the current source I23 is supplied to the current switching consisting of the BipTrs Q21 and Q22.
In this case, when data inputs EIN and EIN/ are input, one of the BipTrs Q21 and Q22 for which a high level signal is input as a base input is turned on (is in conductive state), the other for which a low level signal is input as the base input is turned off (is in non-conductive state). Potential drop due one of load resistors R21 and R22 connected to the BipTr in on-state is increased causing its collector potential to go to the low level, and potential drop of the resistor connected to the BipTr in the off-state is decreased (or not decreased) bringing its collector potential to the high level. In this way, a potential difference is generated in the collector potentials of the BipTrs Q21 and Q22, which is received by the emitter follower of the BipTrs Q23 and Q24 and is output as a potential difference of the outputs EOUT and EOUT/.
This condition is the through state of the latch circuit so that it operates in a manner similar to a general ECL logic buffer.
In the latch state, the latch switching signal ECLK/ goes to the low level and the ECLK goes to the high level, the current switch consisting of the BipTrs Q25 and Q26 is activated and the current switch consisting of the BipTrs Q21 and Q22 is deactivated.
The collector of the BipTr Q25 which inputs by feedback the output signal EOUT to the base, out of the BipTrs Q25 and Q26 constituting a current switch, is connected to the collector of the BipTr Q21 and its signal is input to the base of the BipTr Q23 constituting an emitter follower circuit which outputs the output signal EOUT/ from the emitter. The collector of the BipTr Q26 which inputs by feedback the output signal EOUT to the base is connected to the collector of the BipTr Q22 and its signal is input to the base of the BipTr Q24 constituting an emitter follower circuit which outputs the output signal EOUT from the emitter. Because of this, the BipTr Q25 or Q26 whose collector is connected to the collector of the BipTr Q21 or Q22 whose collector is on the low level side, is turned on so that it goes to the latched state and is capable of holding the data (for example, when the collector potential of the BipTr Q21 is at the low level, the BipTr Q25 is turned on, and its collector potential is held at the low level).
This kind of circuit configuration has been described in, for example, "Digest of Technical Papers, pp. 38-39, ISSCC, 1989".
One of the factors which determine the operating speed of a latch circuit using the conventional ECL current switch described in the above is the response speed of the common collector terminal. If this terminal fails to operate at high speed, it will become meaningless even if the driving capacity of the subsequent emitter follower is enhanced (not possible to achieve a high speed operation). However, the capacity of this terminal is increased because of its being connected to a current switch for latching, which becomes a factor for obstructing a high speed operation.
Moreover, there is still another problem that in example of circuit where many BipTr are used the area occupied by the latch circuit as a whole becomes large because of the large area of a single element of the BipTr.
When considering a recent trend in which synchronous circuits where register circuit employing two latch circuits are controlled by clocks used for input and output, multibit configurations in which the number of data input and output is increased, and the like are introduced, the above fact is becoming an important element of problems for determining the chip area.